Field of the Invention: The present invention relates to digital logic devices used in integrated circuits. More specifically, the present invention relates to digital logic gates, such as inverters, buffers, NAND gates and NOR gates, with extremely skewed trip points and reset circuitry for propagating fast signal edges. Additionally, the present invention relates to circuits, substrates, systems and methods incorporating digital logic gates with extremely skewed trip points.
State of the Art: Advances in semiconductor manufacturing technologies have allowed digital integrated circuit designers to place several million transistors interconnected on a single substrate. Concurrently, advances in computer architecture and particularly processor architecture have driven ever-shorter cycle times. These advances in semiconductor manufacturing and processor architecture have forced digital integrated circuit designers to consider new ways of implementing basic circuit functions, particularly for low-power and high-speed applications.
In metal oxide semiconductor (MOS) devices, the speed of operation is limited by the resistance of a given MOS transistor driving the capacitance (input load) of the next MOS transistor. The output current of an MOS transistor is proportional to its channel width. Thus, if a narrow channel transistor is used to drive a high capacitance load, a relatively long delay results. To reduce this delay in digital circuits, a series of cascaded inverters is frequently used. For example, see U.S. Pat. No. 5,343,090, explicitly incorporated herein by reference for all purposes.
Increasing clock frequency is another approach to reducing cycle times. However, by increasing clock frequencies, fewer (or shorter) logic gate delays are permitted during each clock cycle. To accommodate this need for shorter gate delays, a number of circuit technologies have been implemented for high-speed operation.
Static full complementary metal-oxide semiconductor (CMOS) logic provides two types of transistors, a p-type transistor (PMOS) and an n-type transistor (NMOS). The terms “device” and “structure” used herein to describe CMOS logic include PMOS and NMOS transistors. FIG. 1 illustrates a conventional inverter 100 constructed from CMOS logic. FIG. 2 is a timing diagram for conventional inverter 100 illustrating input signal IN and output signal OUT. Additionally, input gate loading is shared between devices 102, 104 that generate rising and falling edges of a conventional CMOS inverter.
Dynamic logic structures, e.g., domino logic devices, propagate signal edges much quicker than static full CMOS logic. “Domino logic” refers to a circuit arrangement in which there are several series-coupled logic stages having precharged output nodes. The output node of an individual logic stage is precharged to a first logic level. Logic signals are then applied such that, depending on the logic function being implemented and the state of the various input signals, the output node can be switched to a second logic level. As each domino stage in the chain evaluates, the output of the next domino stage may be enabled to switch. However, problems with domino logic include the necessity for precharge circuitry and charge sharing induced noise.
There is a need in the art for digital logic devices capable of propagating selected signal edges more rapidly than conventional CMOS inverters, with virtually all of the input gate loading (capacitance) devoted to the devices that generate a fast edge being propagated, and without the charge sharing induced noise problem associated with domino logic.